Synthesis of multiple-input translinear element networks

We describe two systematic procedures for synthesizing mutlipleinput translinear element (MITE) networks that produce an output current that is equal to product of a number of input currents, each of which is raised to an arbitrary rational power. By using the first procedure, we obtain a MITE network, called a two-layer network, that is relatively insensitive to mismatch in the MITE weight values. By using the second procedure, we arrive at a MITE network, called a cascade network, that reduces the fan-in required of each MITE. We illustrate each of these procedures with an example. 1. MITE NETWORKS: THE SYNTHESIS PROBLEM We recently introduced a class of translinear circuits, called multiple-input translinear element (MITE) networks, that accurately embody product-of-power-law relationships in the current signal domain [1–3]. The MITE is a circuit primitive that produces an output current that is exponential in a weighted sum of the MITE’s input voltages [2, 4]. For a given product-of-power-law relationship, MITE networks often require fewer transistors than would translinear-loop circuits [5, 6]. In some cases, MITE networks can operate on a lower power-supply voltage than could corresponding translinear-loop circuits. Here, we describe two systematic procedures for synthesizing MITE networks to implement any given product-of-power-law relationship between a single output and any number of input currents for which the power-laws are rational numbers. Using the first of these procedures, we obtain a MITE network, called a two-layer network, that is relatively insensitive to mismatch in the MITE weight values. Using the second procedure, we obtain a MITE network, called a cascade network, that reduces the fan-in required for each MITE. We now define the scope of the synthesis problem that we shall consider in this paper. Suppose that we are given an expression relating a single output current, IN+1, to N input currents, I1 through IN, of the form